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Electronic Devices Architectures for the NANO CMOS Era

11 View(s), published at 2009, written by Simon Deleonibus, published by Pan Stanford Publishing
Electronic Devices Architectures for the NANO CMOS Era

Electronic devices architectures for the nano-cmos era by Simon Deleonibus In-depth and timely, this examination gives a state-of-the-art overview by internationally-recognized researchers of the electronic device architectures required for the NanoCMOS era and beyond. Chall.... Published date on: 2009 with total page: 425 pages. Publisher of Electronic Devices Architectures for the NANO-CMOS Era is Pan Stanford Publishing.

In-depth and timely, this examination gives a state-of-the-art overview by internationally-recognized researchers of the electronic device architectures required for the NanoCMOS era and beyond. Challenges relevant to the scaling of CMOS Nanoelectronics are addressed through the different Core CMOS and Memory Devices options in the first part of the book. The second part reviews the New device Concepts for Nanoelectronics Beyond CMOS. What are the fundamental limits of core CMOS, and can we improve the scaling by the introduction of new materials or processes? Will the new architectures using SOI, multigates, or multichannels improve the trade-off between performance and power consumption and relax the constraints of new material integration? Can quantum computing replace binary-based protocols to enhance the information processing power? These questions and others are answered in this book.

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